In general, in the case of a DRAM (Dynamic RAM) used as a main memory device of a computer, for instance, various control signals such as RAS (row access) signal, CAS (column access) signal, etc. are required. Conventionally, these control signals have been so far formed by processing a clock signal supplied as a signal for operating to the computer or CPU.
On the other hand, recently, the operating speed of the CPU has been improved to such an extent as to exceed that of the DRAM. Therefore, in a mini-computer or a work station composed of the CPU and the DRAM, the problem caused by the difference in operating speed between the two has been so far solved by use of the main memory constructed in the form of a plurality of banks (blocks) composed of DRAMs or in accordance with interleave operation of the memory. In this method of using the memory, however, the memory control procedure is complicated and thereby the cost of the memory increases inevitably.
On the other hand, another construction such that the memory is controlled internally in accordance with pipeline operation has been proposed. Where the memory is controlled in accordance with the simple pipeline operation, however, since the memory speed is determined by the data read speed from a core section, the pipeline method does not necessarily contribute to an improvement of the operating speed, so that a specific countermeasure must be taken for the memory control system to increase the memory speed to such an extent as to correspond to the CPU speed.
As described above, in the conventional synchronous LSI memory device, when the above-mentioned conventional memory operating methods such as interleave or bank switching, etc. are applied to a relatively small scale system such as a mini-computer or a work station, there exist problems in that the system cost is increased or down sizing is not attained. In addition, when the operating speed of the CPU is increased more and more as beyond 50 or 100 MHz, since the memory hierarchical structure must be constructed more ingeniously so as to use the CPU properly, with the result that the system is further complicated. For the reason as described above, there exists so far a strong need of memory structure and/or the memory control system which can match the operating speed of the CPU with that of the memory device.